Board-level electrical interconnects §
Board-level interconnects are the copper traces on a PCB and the through-hole or BGA package pins that connect chips to each other and to the board edge. They are relevant whenever a system must move data between a CPU and its memory, between a CPU and a peripheral (GPU, NIC, SSD), or between a microcontroller and a sensor. At the cm scale, the dominant physics is impedance-matched transmission-line behaviour, and the design discipline is PCB stackup and signal-integrity engineering.
Authoritative sources
The interactive simulation below shows how a signal propagates along a PCB trace and reflects at an impedance discontinuity—the central signal-integrity problem at this scale.
Memory interfaces (DDR5, HBM3, LPDDR5) §
Definition. A memory interface is a point-to-point (or shared-bank) electrical link between a memory controller on the CPU/SoC and a DRAM chip or stack. DDR5 uses a 64-bit (x8 × 8) channel per DIMM, split into two independent 32-bit sub-channels; HBM3 stacks 8–16 dies vertically with a 1024-bit wide bus.
Details
DDR5 (2020) operates at 4800–6400 MT/s per pin. The 64-bit channel is split into two independent 32-bit sub-channels, each with its own command/address bus, allowing the controller to issue a new command to one sub-channel while the other is still completing a transfer (lower effective latency). The data pins (DQ) are single-ended; the clock (CK) and data strobe (DQS_t/DQS_c) are differential pairs on controlled-impedance traces (typically 50 Ω single-ended, 85 Ω differential).
Example. A dual-channel DDR5-5600 system has two 64-bit channels, each at 5600 MT/s, giving a peak bandwidth of 2 × 64 × 5600 / 8 = 89.6 GB/s.
HBM3 (2020) stacks DRAM dies vertically using TSVs (through-silicon vias). The 1024-bit bus at 6.4 Gb/s per pin gives 819 GB/s per stack. The interface is so wide that it is effectively a parallel bus, but the TSVs are short enough (~100 µm) that the signal is still in the RC-delay regime rather than the transmission-line regime.
LPDDR5 (2019) is the mobile variant: 16-bit channel, lower voltage (1.05 V), and a smaller pin count for battery-powered devices.
The reader looking for where these interfaces sit in the full memory hierarchy (latency, capacity, bandwidth trade-offs) should consult Memory Hierarchy.
Example problem
A server has 8 DDR5-4800 DIMMs in 4 dual-rank channels. What is the peak memory bandwidth?
Solution
Each channel is 64 bits wide at 4800 MT/s: 64 × 4800 / 8 = 38.4 GB/s per channel. With 4 channels: 4 × 38.4 = 153.6 GB/s peak bandwidth. (Dual-rank does not change bandwidth; it increases capacity.)
Moving from the dedicated memory link to the general-purpose peripheral interconnect, the next class of board-level interconnects connects the CPU to everything else on the board.
PCIe (Peripheral Component Interconnect Express) §
Definition. PCIe is a serial, point-to-point, packet-based interconnect using differential signalling, governed by the Link Training and Status State Machine (LTSSM). It connects the CPU to peripherals (GPU, NVMe SSD, NIC) and supports Gen 1 (2.5 GT/s) through Gen 6 (64 GT/s) with PAM4 modulation.
Details
PCIe replaced the parallel PCI bus in 2003. Each “lane” is a pair of differential signals (TX+/TX−, RX+/RX−). A ×16 link has 16 lanes, giving 16 × 64 Gb/s = 1024 Gb/s = 128 GB/s in one direction at Gen 6.
The protocol is layered: the physical layer (PHY) handles 128b/130b encoding and equalisation; the data link layer handles ACK/NAK and flow control; the transaction layer handles TLPs (Transaction Layer Packets) with addressing and ordering.
Example. An NVIDIA RTX 4090 uses a PCIe Gen 4 ×16 link: 16 × 16 Gb/s = 256 Gb/s = 32 GB/s per direction. The GPU’s HBM2e memory (1 TB/s) is much faster than the PCIe link, so the PCIe interface is the bottleneck for data transfer between host and GPU.
CXL (Compute Express Link, 2019) extends PCIe with cache-coherent, peer-to-peer semantics: a CXL device can snoop the host’s cache, enabling memory pooling and load-balancing across devices.
Example problem
A NVMe SSD uses a PCIe Gen 4 ×4 link. What is the maximum sequential read throughput?
Solution
PCIe Gen 4 is 16 GT/s per lane. With 128b/130b encoding, the effective data rate is 16 × 128/130 ≈ 15.7 Gb/s per lane. With 4 lanes: 4 × 15.7 = 62.8 Gb/s ≈ 7.85 GB/s. In practice, NVMe Gen 4 ×4 drives achieve ~7 GB/s sequential reads.
Stepping down from the multi-gigabit serial links of PCIe, the next class of board-level interconnects are the low-speed control buses that configure and monitor the system.
Low-speed control buses (SPI, I²C, UART, CAN) §
Definition. SPI (Serial Peripheral Interface) is a synchronous, master-slave, 4-wire (SCLK, MOSI, MISO, CS) bus. I²C (Inter-Integrated Circuit) is a synchronous, multi-master, 2-wire (SDA, SCL) bus with address-based arbitration. UART (Universal Asynchronous Receiver-Transmitter) is an asynchronous, point-to-point, 2-wire (TX, RX) serial link. CAN (Controller Area Network) is a differential, multi-master, 2-wire (CAN_H, CAN_L) bus with non-destructive bit-wise arbitration.
Details
These buses operate at low speeds (100 kHz to 100 MHz) and are used for control, configuration, and low-bandwidth data (sensors, EEPROMs, debug consoles, automotive ECUs).
Example. A microcontroller reads a temperature sensor over I²C at 400 kHz (fast mode). The sensor’s 7-bit address is 0x48. The master sends START, the address byte (0x91 for read: 0x48 << 1 | 1), then reads 2 bytes of data.
SPI is faster (up to 100 MHz) but requires a dedicated CS line per slave. I²C is slower but supports many slaves on two wires. UART is the simplest: no clock, no address, just a baud rate agreed upon by both sides. CAN is designed for automotive use: its differential signalling (CAN_H, CAN_L) and non-destructive bit-wise arbitration make it robust to EMI in a car’s electrical environment.
Example problem
An I²C bus has 4 devices with addresses 0x50, 0x51, 0x60, 0x61. The master wants to read from 0x60. How many bits does the master transmit before the first data byte arrives?
Solution
The master transmits: START (1 bit) + address byte 0xC1 (8 bits, 0x60 << 1 | 1 for read) + ACK (1 bit) = 10 bits. Then the slave sends the first data byte. So 10 bits of master transmission precede the first data byte.
Finally, as the industry moves toward chiplet-based designs, the interconnect boundary shifts from the PCB to the package itself, giving rise to die-to-die links.
Die-to-die and chiplet links (UCIe) §
Definition. UCIe (Universal Chiplet Interconnect Express) is an open standard for die-to-die interconnects within a package. It specifies up to 32 GT/s per lane over microbumps (short-range, < 1.5 mm) or TSVs (standard-range, 1.5–50 mm), with a protocol layer compatible with CXL and PCIe.
Details
The chiplet revolution (AMD EPYC 2017, Intel 2023) made die-to-die links a major design concern. UCIe 1.1 (2023) standardises the physical and protocol layers so that chiplets from different vendors can be mixed in a package.
Example. AMD EPYC 9004 (Genoa) has 12 CCDs linked via Infinity Fabric over organic substrate. Intel’s 2023 Meteor Lake uses a tile-based design with compute, GPU, SoC, and I/O tiles linked by Foveros 3D packaging.
The engineering regime is intermediate: the distance (1–10 mm) is too long for on-chip RC-delay modelling but too short for full transmission-line design. The dominant concern is bump/TSV parasitics and package-level crosstalk.
See Interconnect and packaging for the fabrication side.
Example problem
A UCIe ×64 link operates at 32 GT/s per lane. What is the raw bandwidth in one direction? Compare it to a PCIe Gen 5 ×16 link.
Solution
UCIe ×64 at 32 GT/s: 64 × 32 Gb/s = 2048 Gb/s = 256 GB/s per direction. PCIe Gen 5 ×16 at 32 GT/s with 128b/130b encoding: 16 × 32 × 128/130 ≈ 503 Gb/s ≈ 62.9 GB/s per direction. UCIe delivers roughly 4× the bandwidth of a PCIe Gen 5 ×16 link, which is why chiplet-to-chiplet communication can sustain memory-bandwidth-class data rates within a package.
Quiz §
Example problem
A system has a CPU connected to a GPU via PCIe Gen 5 ×16 and to a NVMe SSD via PCIe Gen 4 ×4. The GPU wants to read a 1 GB texture from the SSD. What is the minimum transfer time over PCIe (ignoring protocol overhead)?
Solution
The SSD is connected via PCIe Gen 4 ×4: 4 × 16 GT/s × 128/130 ≈ 62.8 Gb/s ≈ 7.85 GB/s. To transfer 1 GB: 1 / 7.85 ≈ 127 ms. (The GPU’s PCIe Gen 5 ×16 link is faster, so the SSD’s link is the bottleneck.)