Interconnect and packaging §

Packaging is a sequential process: each step prepares the geometry the next step needs. The die cannot be wire-bonded before it is fixed to the die pad; it cannot be molded before the wires exist, or the wires would be frozen in place and untestable; it cannot be tested before singulation because dies on the wafer share common test resources only at wafer level.

The steps, in order:

1. Die attach — the back of the die is fixed to the die pad or substrate (see Die attach below).
2. Interconnect — the die pads are connected to the package: wire bonding or flip-chip (C4) bonding.
3. Underfill — for flip-chip only, an epoxy is wicked under the die to couple it mechanically to the substrate.
4. Molding / encapsulation — the die and wires are buried in epoxy molding compound, or a metal/ceramic lid is sealed over them.
5. Singulation — packages are processed many-at-a-time on a lead frame or reconstituted wafer; a saw or punch separates them.
6. Final test — electrical test, burn-in, and speed binning; the package is now a shippable unit.

Worked example — a 7 × 7 mm QFP microcontroller. The die is glued with silver-filled epoxy to the copper die pad of a 208-lead frame (step 1). A wire bonder connects 208 die pads to the 208 leads with 25 µm Au wire (step 2, about 2 s per die on a modern bonder). No underfill is used for wire-bonded packages (step 3 skipped). The lead frame strip passes through a transfer-molding press that fills an epoxy cavity around each die (step 4). The strip is sawn into individual packages (step 5), which then go through a 125 °C burn-in for 48 h and an ATE test that sorts them by maximum clock frequency (step 6).

For the advanced-packaging variant of this flow (interposer, chiplets), see Advanced packaging below; the same six steps apply, with the interposer itself first “die-attached” to the substrate.

Authoritative sources: the JEDEC JEP95 registrations define the standard package outlines that this flow produces.

Wire bonding is the oldest and still the highest-volume die-to-package interconnect method. A capillary tool threads a wire, melts its tip into a ball (by electric flame-off spark), presses the ball onto the die pad with ultrasonic vibration and force (the ball bond), then pulls the wire through a loop profile and presses the wire flat onto the second pad (the stitch bond). The wire is then torn off and the cycle repeats at 10–20 bonds per second.

• Ball bond: the first bond of each wire; the ball is roughly 2–3× the wire diameter, which is why the ball bond sets the minimum pad pitch.
• Stitch bond: the second, ball-less bond of the same wire — simply the flat continuation of the wire where it terminates on the lead. A wire always makes one ball bond and one or more stitch bonds; “stitch bonding” is not a separate high-density technology, it is just the tail end of every wire.
• Bond pitch: the center-to-center distance between pads. Minimum ~80 µm for Au ball bonding; ~50 µm for Cu (Cu allows smaller balls and finer pitch, but needs an inert atmosphere because Cu oxidizes).
• Limitation: each wire is a series inductance of roughly 1–2 nH/mm, which limits signal speed; and the loop geometry means wires cannot be packed at flip-chip densities.

Worked example — bonding a 64-pad die. A die has 64 pads at 90 µm pitch along one edge. The bonder forms a ball on pad 1, loops over the ~1.5 mm gap to the lead frame, places a stitch bond, tears, and moves to pad 2. At 15 bonds/s the whole die takes 64/15 ≈ 4.3 s. The 2 mm long wires contribute ~2–4 nH each — negligible for a 32 kHz watchdog timer, unacceptable for a 10 Gb/s serializer, which is why high-speed I/O moved to flip-chip.

Authoritative sources: package outlines for wire-bonded families are registered in JEDEC JEP95.

Solder is a low-melting alloy that wets clean metal surfaces and freezes into a joint that is both electrical and mechanical. In electronics the workhorse is SAC305 (Sn-96.5/Ag-3.0/Cu-0.5), liquidus 217 °C. The joint is made in a reflow oven: the assembly is heated on a controlled profile — ramp to 150–180 °C (solvent evaporation, flux activation), a soak that lets the whole board equalize, a short peak of 245–260 °C that melts the solder for 30–90 s, and a controlled cool-down that freezes the joint as fine, fatigue-resistant grains.

Two joint families on this page use exactly this physics at different scales:

• C4 bumps: solder preforms (75–200 µm diameter) are placed on the die pads and substrate pads, then reflowed; surface tension self-aligns the die to within a few µm (see Flip-chip (C4) bonding).
• BGA balls: solder spheres (0.3–1.0 mm) on the substrate bottom attach the package to the PCB — the same reflow, one level up.

Worked example — reflowing a BGA package onto a PCB. A 35 mm FCBGA with 4000 balls enters the oven. During soak the large package lags the small resistors around it by tens of degrees; the 60–90 s soak lets it catch up so that every ball reaches liquidus during the peak. Peak is set to 250 °C: 33 K above liquidus (enough to wet and collapse the balls) but below the 260 °C limit that moisture-sensitive package mold compound can tolerate. After cooling, the collapsed balls are ~0.4 mm tall and hold the package 0.4 mm above the board.

• Reliability: thermal cycling makes the PCB (CTE ~17 ppm/K) and package (CTE ~7–15 ppm/K) expand differently, fatiguing the solder joints. Joint life is predicted by Coffin-Manson or Darveaux models.
• The board itself — laminating, patterning, drilling — is covered in PCB fabrication; mounting components onto that finished board is the reflow process described here.

In flip-chip, all pads connect at once during one reflow, instead of one-at-a-time as in wire bonding. The die is picked up, flux-dipped or flux-printed, placed bump-down on the substrate with a few µm of accuracy, and heated. As the solder melts, the surface tension of each molten blob pulls the die into alignment — this self-alignment is the key physics: the die corrects placement errors of up to ~50% of the bump diameter for free. The joint solidifies as a slightly squashed sphere whose height is set by the bump volume and the die weight.

• Bond pitch: 130–300 µm for C4 bumps; 25–55 µm for micro-bumps (used between dies stacked with TSVs, and on silicon interposers).
• Advantage: the interconnect is the bump itself — under 100 µm long, versus millimeters of wire — so inductance drops by an order of magnitude and I/O density rises by two orders of magnitude.
• Underfill: silicon (CTE 2.6 ppm/K) and organic substrate (CTE ~15 ppm/K) expand at different rates; the rigid bumps would shear-fatigue. A capillary-flow epoxy wicks under the die and couples them mechanically, spreading the strain.
• Use: mobile SoCs, GPUs, FPGAs — any die with more I/O than wire pitch allows.

Worked example — bonding a 1000-bump die. A 10 × 10 mm die has 1000 signal/power pads at a 150 µm C4 pitch. The bonder dispenses flux, places the die (accuracy ±10 µm — the reflow self-alignment absorbs it), and the substrate carrier passes through a reflow profile peaking at 245–260 °C. The bumps collapse from ~100 µm spheres to ~60 µm tall joints. Capillary underfill is dispensed along two edges, wicks across the 60 µm gap in ~30 s, and cures at 150 °C. The die is now electrically connected at 1000 I/O with a total interconnect inductance of ~0.05 nH per bump — versus ~2 nH per wire bond.

Authoritative sources: IPC-7095E (BGA and flip-chip design and assembly); JEDEC DG-414 (BGA package design requirements).

The interconnect technologies above are too thin or too compliant to hold the die against shock, vibration, and shear — so the die is attached separately, from the back. Three attachment materials dominate:

• Silver-filled epoxy adhesive: the default for plastic packages. An epoxy loaded 70–85% with Ag flakes: electrically and thermally conductive, cured at 150–175 °C, bond line 20–50 µm. Cheap, low temperature, but softens near 150–200 °C.
• Solder die attach (eutectic): a solder layer (e.g., AuSn at 280 °C, or PbSn) melts and wets the die’s backside metallization. Used for power devices and high-reliability packages because the joint conducts heat far better and survives higher junction temperatures.
• Anisotropic conductive film (ACF): a film full of Ni/Au spheres that conducts vertically only — the spheres are trapped and deformed between opposing pads, and insulate laterally. Used when the die has fine-pitch pads on the attachment plane itself (display driver ICs bonded to glass, camera modules).

Worked example — power MOSFET in a D²PAK. The die dissipates 30 W. A silver-filled epoxy bond line of 40 µm at ~7 W/(m·K) over a 10 mm² die would add R = t/(kA) = 40 µm / (10 mm² × 7 W/(m·K)) ≈ 0.08 K/W — acceptable. But at 200 °C junction temperature the epoxy approaches its glass transition, so a solder die attach (AuSn, k ≈ 57 W/(m·K)) is chosen instead, cutting the bond-line resistance to ~0.01 K/W and surviving the temperature.

Authoritative sources: package outlines and die-pad dimensions for attached-die packages are registered in JEDEC JEP95.

Bare silicon with 25 µm wires cannot survive handling, moisture, or alpha particles. Encapsulation gives the package its mechanical body, blocks moisture and ionic contamination, and (for opaque compounds) blocks light that would photogenerate carriers in the die.

• Transfer molding: the dominant process. A pellet of epoxy molding compound (EMC) — fused silica filler (~70–85%) in epoxy resin — is heated to ~175 °C, becomes viscous, and is pressed (transferred) into a mold cavity around the lead-frame strip with dies and wires already inside. The filler lowers the CTE to match silicon and copper and slows moisture uptake. Hundreds of packages are molded per press cycle.
• Lids and heat spreaders: power packages (CPUs, FPGAs) get a metal integrated heat spreader (IHS) — a Cu or Al cap attached to the package substrate with solder or adhesive, with a thermal interface material between lid and die top. The IHS is a package lid, not a bond to the die itself; it spreads the die’s heat flux over a flat, large area for the heat sink. Hermetic packages (ceramic, metal-can) use a welded or brazed lid for military/aerospace-grade moisture exclusion.
• Moisture sensitivity: EMC absorbs water; at reflow the trapped moisture flashes to vapor and delaminates the compound (“popcorning”). Packages are rated MSL 1–6 by JEDEC J-STD-020 and must be baked before reflow if floor-life is exceeded.

Worked example — molding a QFP strip. A 208-lead QFP strip of 50 units is loaded into a mold. Two EMC pellets of ~5 g each are preheated to 80 °C, transferred at 70 kg/cm² into the cavities at 175 °C, and cured in-mold for 90 s, then post-cured 4 h at 175 °C. The silica filler brings the compound CTE to ~10 ppm/K, between Si (2.6) and Cu (17), so the encapsulated wires are not over-stressed during temperature cycling.

Authoritative sources: JEDEC JEP95 defines the molded package outlines; moisture-sensitivity classification is JEDEC J-STD-020.

A TSV is a copper-filled hole drilled through the silicon, so a signal can enter the top of a die and leave its bottom — the prerequisite for stacking dies vertically. The stack is built by bonding die-on-die (or wafer-on-wafer) with micro-bumps, so the TSVs of all dies line up into a vertical signal path.

• Diameter: 2–10 µm; depth: 30–100 µm (the thinned die thickness).
• Fabrication: Etching (DRIE / Bosch process) drills the via; Deposition (PVD or electroplating) fills it with Cu; the top and bottom surfaces are planarized by Surface finishing.
• Use: 3D DRAM (HBM), logic-DRAM stacks, power management ICs.
• Challenge: TSVs consume die area; the aspect ratio limits the minimum diameter.

Worked example — an HBM stack. An HBM3E stack has 8 DRAM dies (each ~45 µm after thinning) plus 4 base-die TSV layers, for ~500 µm total. Each DRAM die carries ~1000 TSVs at 2–5 µm diameter. The TSVs are drilled before thinning (via-middle process), filled by electroplating, and the wafer is then ground from 775 µm to ~45 µm — thin enough that the TSV bottoms are exposed for micro-bump bonding. The stack’s vertical interconnect length is ~500 µm total, versus ~5 mm if the same dies were wired side-by-side.

Authoritative sources: TSMC CoWoS / 3DFabric covers interposer and stacking technology; IPC-7095E covers assembly reliability.

When one reticle-sized die becomes too large to yield economically, or when logic and memory want different process nodes, the monolithic die is split into chiplets assembled side-by-side (2.5D) or stacked (3D) inside one package. The interposer is the piece of substrate that carries the fine-pitch die-to-die routing that an organic package substrate cannot.

• Organic interposer: a multi-layer PCB-like substrate with fine-pitch routing. Used for FCBGA (flip-chip ball grid array) packages.
• Silicon interposer: a thin Si wafer with TSVs and fine-pitch routing. Used for CoWoS (Chip-on-Wafer-on-Substrate) packages (e.g., NVIDIA, AMD GPUs).
• Chiplet architecture: a large die is split into smaller dies (chiplets) of different functions and process nodes, then assembled on an interposer. Reduces cost and yield loss.
• 2.5D vs 3D: 2.5D places dies side-by-side on an interposer; 3D stacks dies vertically with TSVs.
• Hybrid bonding: Cu–Cu direct bonding with dielectric adhesion; the successor to micro-bumps for sub-10 µm pitch die-to-die interconnect (HBM4, logic-logic stacks).

Worked example — routing budget on an interposer. A logic die and an HBM stack sit 5 mm apart on a silicon interposer. The die-to-die interface needs 1024 signals at 32 Gb/s. At a 55 µm micro-bump pitch with 2:1 signal-to-power, the interface edge needs 1024 × 2 × 55 µm ≈ 113 µm of bump-row width — trivially routable in the interposer’s 3–4 metal layers at 0.4 µm lines. The same 1024 links over wire bonds would need ~1024 × 80 µm ≈ 8 cm of die edge — impossible. The interposer is what makes chiplet bandwidth affordable.

Authoritative sources: TSMC CoWoS (silicon interposer technology); JEDEC DG-414 (BGA package design requirements).

Heat conduction follows Fourier’s law: heat flows from hot to cold in proportion to the temperature gradient, and each material layer in the path adds a thermal resistance R = t/(kA) (thickness over conductivity times area). The fundamentals — thermal resistance, conduction, and the heat equation — are developed in Thermodynamics; packaging applies them in a fixed, layered geometry.

The die’s heat leaves through a series chain of layers, and the worst layer (lowest k·A) dominates:

• Thermal interface material (TIM): a high-conductivity paste or pad between the die (or IHS) and the heat sink. Typical thermal conductivity: 3–15 W/(m·K) for pastes, 5–20 W/(m·K) for pads. TIMs exist because mating surfaces touch at only ~1% of their nominal area (roughness); the TIM fills the remaining 99% of air (k = 0.026 W/(m·K)), which would otherwise dominate the stack.
• Integrated heat spreader (IHS): a metal cap (Cu or Al) attached to the package substrate, with a TIM between the lid and the die top; it provides a flat, uniform surface for the heat sink and protects the die.
• Thermal vias: TSVs or substrate vias filled with Cu to conduct heat laterally or vertically through the package.
• Cold plate / liquid cooling: for high-power packages (>300 W), a liquid-cooled cold plate is attached to the IHS to remove heat efficiently. (The airflow side of the problem belongs to fluid mechanics, not covered here.)

Worked example — a 200 W GPU die. Die 12 × 12 mm, TIM1 50 µm at 5 W/(m·K): R₁ = 50×10⁻⁶ / (5 × 144×10⁻⁶) ≈ 0.07 K/W. Cu IHS, 2 mm, k = 390: R ≈ 0.04 K/W. TIM2, 100 µm at 8 W/(m·K) over the full 40 × 40 mm lid: R ≈ 0.003 K/W. Heat sink + airflow: ~0.25 K/W. Total ≈ 0.36 K/W, so at 200 W the junction sits at 25 + 72 ≈ 97 °C — just under the 100 °C limit. The dominant term is the air, not the package: improving the paste cannot fix a bad heat sink.

Authoritative sources: JEDEC JEP95 (package outlines incl. thermal pads); IPC-7095E (assembly effects on thermal path).

Most of a package’s joints are hidden — under the die, under the mold, under the BGA balls — so inspection must see through solid materials, and reliability must be proven by stress, not by looking.

• X-ray imaging: solder absorbs X-rays strongly, so voids, bridging, and missing balls in BGA and flip-chip joints show directly. It is the standard inline check for hidden joints.
• Scanning acoustic microscopy (SAM): ultrasound reflects at material interfaces; delaminations between mold compound and die (invisible to X-ray) show as bright echoes. Used for moisture-damage screening.
• Cross-sectioning: destructive — the package is potted in resin, ground to the plane of interest, and polished for optical/SEM inspection of bump height, intermetallic thickness, and wire bonds.
• Warpage: a 60 mm FCBGA substrate can bow hundreds of µm between room temperature and reflow (250 °C), which can lift corner balls off the pads. Warpage is measured shadow-Moïré style over temperature (JEDEC JESD22-B112) and controlled by substrate core symmetry.
• Temperature cycling: packages are cycled (e.g., −40 ↔ +125 °C, JESD22-A104) to fatigue the solder joints; the cycles-to-failure feed the Coffin-Manson/Darveaux life models used in the solder section.
• Preconditioning: moisture soak + reflow (JESD22-A113) simulates floor life before board mounting, to screen for popcorning.

Worked example — a failing BGA lot. A customer sees open joints at the four corners of a 45 mm FCBGA after board assembly. X-ray shows the corner balls did not collapse (still spherical, not squashed). SAM shows no mold delamination. The diagnosis: substrate warpage at reflow peak lifted the corners out of the solder paste before wetting — a warpage problem, not a contamination problem. The fix is a stiffer substrate core and a longer soak zone in the reflow profile, verified by shadow-Moïré warpage measurement to JEDEC JESD22-B112.

Authoritative sources: the JEDEC JESD22 test-method family (A104 temperature cycling, A113 preconditioning, B112 warpage) and IPC-7095E (inspection and rework of BGA/flip-chip assemblies).

1. Architecture: CoWoS (2.5D silicon interposer). The logic die and HBM stacks are placed side-by-side on a silicon interposer with TSVs. The memory controller die is placed on the same interposer.
2. Interposer: ~150 µm thick Si (typical range 100–200 µm), with 3–5 metal layers for routing. TSVs connect the top (die side) to the bottom (substrate side).
3. HBM3E stacks: each stack is a 3D stack of 12 DRAM dies connected by TSVs. The bottom die has C4 bumps that connect to the interposer.
4. Logic die: flip-chip bonded to the interposer with micro-bumps (25–55 µm pitch).
5. Substrate: the interposer is attached to an organic FCBGA substrate (60 × 60 mm, 10–12 layers) with C4 bumps. The substrate has BGA balls on the bottom for PCB attachment.
6. Thermal: a heat spreader (IHS) is attached to the package substrate with a thermal interface material (TIM) between the lid and the die tops. The HBM stacks are cooled by the same heat spreader or by a separate cold plate.