PCB fabrication §

• Core: a solid dielectric (FR-4, polyimide) with copper on both sides. Provides mechanical rigidity.
• Prepreg: a dielectric with copper on one side, used to bond layers together.
• Layer count: 2, 4, 6, 8, 12, 16, or more. Each additional layer pair adds cost and complexity.
• Cure: the epoxy resin cures at 170–190 °C (up to 200 °C for high-Tg materials) under 200–400 psi pressure. The board is then trimmed to outline.

• Subtractive (etching): a dry-film photoresist is exposed and developed to define the trace pattern. The exposed copper is etched away. Industrial etchants include H₂SO₄/H₂O₂, ammonium persulfate (APS), and cupric chloride; FeCl₃ is a small-scale/prototype alternative. See Etching for the underlying chemistry. Minimum trace width ~50 µm (standard) or ~25 µm (HDI).
• Additive (DAP / SAP): a thin seed layer (Cu, 0.5 µm) is deposited by Deposition (electroless or PVD). A photoresist is patterned, and copper is electroplated only on the exposed areas. The resist and seed are stripped. Enables finer traces and better aspect ratios.
• Direct imaging (LDI): a laser directly images the photoresist, eliminating the need for a physical mask. Enables sub-25 µm features.

• Mechanical drilling: a carbide drill (0.15–3.0 mm) drills through-holes. Minimum hole size ~0.15 mm for standard drilling; ~0.05–0.1 mm for laser drilling.
• Laser drilling: a CO₂ or UV laser drills micro-vias (0.05–0.15 mm) for HDI designs. The laser can drill blind or buried vias that do not pass through the full board thickness.
• Plating: the drilled holes are plated with Cu (electroless seed + electroplating) to make them conductive. Minimum plating thickness 20 µm (IPC Class 2) / 25 µm (IPC Class 3).

• Solder mask: a liquid or dry-film epoxy or polyimide, 20–30 µm thick (typical 20–25 µm). Prevents solder from bridging adjacent pads during reflow. Colors: green (most common), black, red, blue, white.
• Silkscreen: a UV-curable ink is screen-printed to label component references, polarity marks, and logos.
• Surface finish: the exposed pad surface is treated to prevent oxidation and ensure solderability. Options: HASL (hot air solder level), ENIG (electroless nickel immersion gold), OSP (organic solderability preservative); see Surface finishing.

• Key parameters: trace width, dielectric constant (Dk) of the prepreg/core, and layer spacing (distance to the reference plane). For a microstrip, the characteristic impedance is approximately:

where h is the dielectric thickness and w is the trace width.

• Material choice: low-Dk prepregs (e.g., Rogers RO4350B, Dk ≈ 3.66) are used for RF layers; standard FR-4 (Dk ≈ 4.3–4.5) is acceptable for digital signals up to several GHz.
• Tolerance: the fab must hold trace width and dielectric thickness to tight tolerances (±5 µm width, ±10 % Dk) to keep impedance within spec.

• V-score: a V-shaped groove is scored on one or both sides; the board snaps apart along the score line. Fast and cheap, but limited to rectangular outlines.
• Routing: a CNC router with a small end-mill cuts the exact board outline. Supports arbitrary shapes, slots, and chamfers.
• Laser cutting: a CO₂ laser ablates the outline. Useful for thin or flexible boards where mechanical stress from routing would damage the board.
• Panelization: multiple boards are fabricated on a single panel (with tooling holes and fiducials) to improve throughput; the panel is de-panelized after all processing is complete.

• AOI (Automated Optical Inspection): high-resolution cameras image both sides of the board to detect solder mask defects, missing silkscreen, copper shorts, and open traces.
• X-ray inspection: cross-section or 2-D X-ray images verify via plating thickness, barrel integrity, and buried-via fill. Critical for HDI and BGA substrates.
• Electrical continuity testing: a flying-probe or bed-of-nails tester checks every net for shorts and opens against the design database (IPC-6012 Class 2/3).
• Impedance testing: TDR measurements on controlled-impedance coupons verify that the stack-up produces the target impedance (see Impedance control).
• Cross-reference: the general SPC and NDT principles behind these checks are covered in Metrology and quality control.

• Flexible layer: polyimide (Kapton) with copper, 0.05–0.1 mm thick. Can be bent repeatedly.
• Rigid layer: FR-4 or polyimide core, 0.2–1.6 mm thick.
• Use: smartphones, cameras, medical devices, aerospace (where space is constrained and the board must flex during assembly or operation).

1. Layer count: 16 layers (8 signal layers, 4 ground/power planes, 2 mixed). FR-4 core with low-Dk prepreg for RF layers.
2. Copper patterning: Additive process (SAP) with LDI. The 100 µm trace width and 100 µm spacing require LDI for accuracy. The additive process avoids the etch-back that would widen the traces in a subtractive process.
3. Vias: 0.1 mm micro-vias drilled by UV laser. Blind vias connect adjacent layers; through-vias connect the outer layers to the inner planes.
4. Plating: Electroless Cu seed (0.5 µm) + electroplated Cu (25 µm minimum) in the vias.
5. Solder mask: Liquid photoimageable solder mask (LPI), 22 µm thick, with 100 µm exposure on the pads.
6. Surface finish: ENIG (electroless nickel 3–6 µm + immersion gold 0.05–0.1 µm) for the RF pads to ensure consistent impedance and solderability.
7. Inspection: AOI (automated optical inspection) for solder mask defects; X-ray for via plating; impedance test on coupon boards.