Etching §

How it works, step by step. The wafer is immersed in (or sprayed with) a liquid etchant. The etchant (1) transports to the surface, (2) reacts with the exposed film, converting it into a soluble product, and (3) the product diffuses away. In a liquid, molecules arrive at the surface from every direction with equal probability, so an amorphous film etches equally fast in every direction: the etch front is a circle expanding from the mask opening, and the etch tunnels under the mask — the undercut — by exactly as much as it goes down. In a single crystal, however, different crystal planes dissolve at very different rates, so the etch becomes anisotropic along crystallographic directions even though the chemistry itself has no preferred direction.

Worked example — KOH V-grooves. KOH etches Si(100) planes about 100× faster than the (111) planes, which make a 54.74° angle with the wafer surface. Etching a window in a Si(100) wafer therefore stops laterally on four (111) planes, producing a pit with perfectly flat 54.7° sidewalls — the basis of MEMS membranes, nozzles and cavities. Conversely, HF dissolving a sacrificial SiO₂ layer under a released MEMS plate is chosen because it is isotropic: it must creep horizontally over long distances to undercut the plate.

Authoritative sources: Sato et al. (1998) measured the orientation-dependent KOH etch rates behind the crystallographic model above; Madou, Fundamentals of Microfabrication covers wet-etching practice in depth.

Step 1 — make a plasma. A gas such as CF₄, CHF₃, SF₆ or Cl₂ is fed into a vacuum chamber and broken into ions and radicals by an RF field (typically 13.56 MHz). Radicals (F, Cl atoms) are neutral and fly in all directions; ions are charged and can be accelerated by electric fields.

Step 2 — two removal mechanisms. Radicals react chemically with the film, forming a volatile product (e.g. Si + 4F → SiF₄↑): fast but isotropic, like a wet etch. Ions accelerated vertically through the sheath (the thin field region above the wafer) sputter and break bonds physically: directional but barely selective. Reactive ion etching (RIE) combines them: ion bombardment clears inhibitor films and breaks bonds only on horizontal surfaces, so the chemical attack proceeds vertically while the sidewalls stay protected — anisotropy from directionality, selectivity from chemistry.

Step 3 — decouple density from energy (ICP). In a simple RIE the same RF power sets both ion density and ion energy. An inductively coupled plasma (ICP) adds a coil that generates the plasma separately, so rate (density) and damage (energy) can be tuned independently.

Step 4 — go deep: the Bosch DRIE process. For trenches deeper than ~10 µm, plain RIE is too slow or too isotropic. The Bosch process (Laermer & Schilp, 1996) alternates two steps many times: a short etch step (SF₆ for silicon — as in MEMS and through-silicon vias; CHF₃ or CF₄ for SiO₂, as in 3D NAND), then a passivation step in which C₄F₈ deposits a ~5–10 nm fluorocarbon film on all surfaces. The next etch step’s ions strip that film from horizontal bottoms but not from vertical sidewalls, so the trench advances vertically — leaving a small lateral scallop per cycle. Aspect ratios above 100:1 are routine.

Step 5 — stop at the right depth. Endpoint detection stops the etch when the target film is gone: a change in plasma optical emission, laser interferometry of the etch front, or a shift in RF impedance.

Worked example — gate-etch selectivity. Etching a 150 nm poly-Si gate over a 2 nm gate oxide with a spec of “remove ≤ 1 nm of gate oxide”: the oxide loss is depth/S, so S = rate(Si)/rate(SiO₂) ≥ 150/1 = 150:1. This is why gate etchers are among the most tightly specified tools in a fab.

Authoritative sources: the Bosch process is described in US Patent 5,501,893 (Laermer & Schilp, 1996); plasma-etching fundamentals are in May & Sze, Fundamentals of Semiconductor Fabrication.

How it works, step by step. An ion gun ionizes argon and extracts a beam accelerated to 100–1000 eV that hits the wafer in vacuum. Each ion transfers momentum to surface atoms; when the transfer exceeds the surface binding energy, an atom is ejected (the sputter yield, typically 0.1–3 atoms per ion). Because the beam is collimated, milling is directional; because there is no chemistry, it etches everything — metals, oxides, diamond, ceramics — with little selectivity beyond differences in sputter yield.

Worked example. Gold is hard to etch chemically (no volatile fluoride or chloride at low temperature), so it is ion-milled: at 500 eV and 1 mA/cm², with a sputter yield of ~1.5 atoms/ion and an atomic density of 5.9×10²² atoms/cm³, the rate is (1×10⁻³/1.6×10⁻¹⁹) × 1.5 / 5.9×10²² ≈ 1.6 nm/s ≈ 95 nm/min. Slow — which is why milling is reserved for thin films and cleaning, not deep patterning.

Limitations: slow, barely selective, and the energetic beam amorphizes the top few nanometres and implants Ar into the surface — acceptable on a back-end metal, unacceptable in a transistor channel.

• Ion damage / implantation: energetic ions (10–200 eV) displace atoms in a 10–50 nm surface layer, degrading carrier mobility and increasing leakage; mitigated by a post-etch anneal or a sacrificial removal layer.
• Charging: insulating films (SiO₂, Si₃N₄) accumulate charge during plasma exposure; the local fields deflect ions, causing non-uniform etching or gate-oxide breakdown.
• Polymer residue: fluorocarbon passivation (C₄F₈) and resist byproducts leave a carbon-rich film, removed by an O₂ plasma or a wet clean.
• Mask erosion (CD loss): the mask is consumed during the etch, and its recession widens the feature. The arithmetic: mask loss = etch depth ÷ selectivity. A 100 nm resist mask with 100:1 selectivity loses 1000 nm / 100 = 10 nm over a 1 µm etch — acceptable. The same 1 µm etch at 10:1 selectivity would consume 1000/10 = 100 nm — the entire mask — before the film was cleared, which is why deep etches require hard masks. The resulting etch bias must be compensated in the Lithography CD budget.
• Sidewall roughness: stochastic ion bombardment and Bosch cycling leave 1–5 nm RMS sidewall roughness, which scatters electrons in narrow interconnects and adds gate-length variability.

How it works, step by step. The wafer is mounted face-down on a rotating carrier and pressed against a rotating polyurethane pad soaked in slurry — abrasive nanoparticles (silica, ceria, alumina) in a chemically active solution. Material is removed by the combination of the two mechanisms this page separates: the chemistry weakens or dissolves the surface (as in wet etching), and the mechanical abrasion of pad asperities and particles scrapes the weakened layer off (a micro-scale ion-milling analogue). The removal rate follows the Preston equation: rate = K_p · pressure · velocity, so removal is fastest exactly where the surface sticks up highest — the process is self-limiting and drives the surface flat.

Why it is needed: every deposition + etch cycle adds topography. After a few metal layers the wafer surface is a mountain range, and Lithography can no longer focus depth-of-focus-tight optics on it. CMP flattens the wafer after every layer (and after the shallow-trench-isolation fill), so that 50–100 cycles can stack up. It is the step that makes planar multi-layer fabrication possible at all.

Worked example. Copper damascene: deposit a barrier + copper seed, electroplate copper to overfill the trenches, then CMP the copper back until only the trench fill remains — the metal lines are defined by the CMP stop, not by an etch. The slurry chemistry is tuned so the removal rate drops sharply on the underlying barrier dielectric (selectivity by chemistry, exactly as in a wet etch).

A 3D NAND flash memory requires 1000 stacked layers of SiO₂/Ta₂O₅, each 10 nm thick, with word-line trenches of aspect ratio 100:1. Which etching process is appropriate, and why can the other two classes not do it?