Technopedia

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Deposition

Deposition adds a thin film of conductor, insulator, or semiconductor material onto a substrate. It is the material-adding step in electronics fabrication: every metal wire, dielectric layer, and semiconductor channel on a chip is deposited.

Authoritative sources

Utility

Role in the fabrication flow

A chip is built layer by layer in a repeating cycle:

  1. Lithography — pattern a resist on the wafer.
  2. Deposition — add the material (this page).
  3. Etching — remove material outside the pattern.
  4. Planarization — flatten the surface by chemical-mechanical polishing (CMP): the wafer is pressed face-down on a rotating pad soaked in an abrasive, chemically reactive slurry, which removes roughly 10–100 nm of the highest topography per pass until the surface is flat again. CMP is needed because each deposition + etch cycle adds height; without it, later lithography could not focus on a flat plane. CMP is a step between deposition and etch in every layer, not a packaging-specific operation.
  5. Repeat for the next layer.

Each cycle adds one functional layer (a gate oxide, a metal interconnect, a well region, etc.). After 50–100 cycles the wafer contains the full 3D stack of a modern logic or memory chip. Deposition is the step that actually adds material; without it the etch and planarization steps have nothing to shape.

Key concepts

Chemical vapor deposition (CVD)

A gas-phase chemical reaction at the heated substrate surface deposits a solid film; variants (thermal, plasma-enhanced, metalorganic) differ only in how the reaction energy is supplied.

Details

How it works, step by step. Precursor gases are flowed into a reactor chamber. They diffuse through a boundary layer to the wafer, adsorb on the hot surface, react there (the surface must be hot enough, or a plasma must crack the molecules), and the solid product stays as film while by-products desorb and are pumped away. The rate is limited either by the surface reaction (temperature-controlled, gives good coverage) or by gas transport (flow-controlled, gives high rate but poor coverage).

Worked example — PECVD silicon dioxide. A fab deposits an interlayer dielectric from SiH₄ + N₂O at 350 °C with a 13.56 MHz plasma. The plasma dissociates N₂O into reactive O and N species, so the oxide grows at ~100 nm/min — about 10× faster than a purely thermal process at the same temperature — while staying below the 450 °C limit that protects doped junctions and metal lines. A 500 nm film therefore takes ~5 min of deposition.

Reactor geometry:

Showerhead CVD reactor showerhead gas distributor (precursor + co-reactant in) heated chuck (200–1100 °C, or RF plasma above) wafer + growing film by-products pumped out (SiH₄ + N₂O → SiO₂ + H₂ + N₂) rate: 10–500 nm/min · conformality: good (step coverage > 90 %)

Main variants:

Reference: Pierson, Handbook of Chemical Vapor Deposition (1999).

Example problem

A PECVD tool deposits SiO₂ at 100 nm/min. How long must it run to fill a 0.5 µm gap between metal lines, and what limits the temperature?

Solution
  • Time = thickness / rate = 500 nm / (100 nm/min) = 5 min.
  • The temperature is limited by the thermal budget of the layers already on the wafer: dopants must not diffuse and aluminum (melting 660 °C) must not be present, so PECVD runs at 200–400 °C, using the plasma to supply the reaction energy instead of heat.

Atomic layer deposition (ALD)

A self-limiting special case of CVD: alternating precursor pulses each saturate the surface, so exactly one atomic layer (a fraction of a monolayer, ~0.1 nm) is added per cycle, independent of how long the pulse lasts.

Details

How it works, step by step. One cycle has four steps: (1) pulse precursor A — its molecules chemisorb on the surface until every reactive site is occupied, then the uptake stops by itself (self-limiting); (2) purge the excess A away; (3) pulse co-reactant B, which reacts with the adsorbed A to form one layer of product and regenerates reactive sites; (4) purge again. Because each step saturates, the growth per cycle (GPC) is fixed by surface chemistry, not by time or gas flow — which is why ALD coats deep trenches and nanowires with atomic uniformity even at aspect ratios of 10:1 to 20:1 (beyond that, purge times must be extended because diffusion into the feature becomes slow).

Worked example — HfO₂ high-k gate dielectric. HfCl₄ + H₂O at 300 °C gives a growth per cycle of ~0.1–0.15 nm (about 10–15 % of one HfO₂ monolayer per cycle, as measured by Puurunen for the analogous TMA/H₂O system). To grow a 5 nm gate dielectric: 5 nm / 0.12 nm per cycle ≈ 42 cycles. Each cycle takes ~5–10 s, so the film takes a few minutes — slow, but the thickness control is ±1 % across the wafer.

One ALD cycle:

1. Pulse A A chemisorbs to saturation 2. Purge excess A removed 3. Pulse B B reacts: one layer forms 4. Purge new sites ready: +1 cycle

Reference: Puurunen, J. Appl. Phys. 97, 121301 (2005).

Example problem

An ALD process for Al₂O₃ from TMA/H₂O grows 0.11 nm per cycle. How many cycles for a 20 nm capacitor dielectric, and why does extending the TMA pulse time not make the film thicker?

Solution
  • Cycles = 20 nm / 0.11 nm ≈ 182 cycles.
  • Extending the pulse does not help: once every surface hydroxyl site has reacted with TMA, additional molecules find no reactive sites and are simply purged away. The reaction is self-limiting — the GPC is set by surface chemistry, not by dose.

Physical vapor deposition (PVD)

A solid source is vaporized in vacuum and condenses on the substrate; atoms travel in straight lines, so coverage of shadowed regions is limited.

Details

How it works, step by step. The source material is turned into vapor — by heating it (evaporation) or by bombarding it with energetic ions (sputtering). Because the chamber is at high vacuum, the atoms fly without collisions and land on whatever surface has a direct line of sight to the source. Film growth is therefore directional: horizontal surfaces get thick films, trench bottoms get thin ones. A magnetic field (magnetron) traps electrons near the target so more Ar⁺ ions are created, raising the rate.

Worked example — sputtered aluminum interconnect. An Al target is sputtered with Ar⁺ at 300 W in 1 mTorr of argon; the wafer sits 5 cm away at ~150 °C. Atoms leave the target over a broad angular distribution, so the step coverage on a 1 µm deep via is ~30–60 % at the bottom — which is why sputtered metal needs a conformal ALD/TiN liner first, and why modern damascene flows deposit Cu by electroplating instead. Typical sputter rate: 1–10 nm/min per kW-class power.

Sputtering geometry:

Magnetron sputtering target (cathode, −400 V) Ar⁺ ejected atoms (line-of-sight) wafer — thick film on top surfaces, thin in trenches

Main variants:

Example problem

A sputter tool deposits TiN at 4 nm/min. A barrier of 10 nm is needed on the via bottom, but the step coverage at the bottom of a 1 µm deep, 0.3 µm wide via is only 30 %. What bottom thickness results from a nominal 10 nm deposition, and how is the shortfall fixed?

Solution
  • Bottom thickness = 30 % × 10 nm = 3 nm — too thin to block Cu diffusion.
  • Fixes: rotate the wafer and add collimation or ion-beam assistance to narrow the angular distribution; or switch to a conformal method (ALD TiN, ~0.1 nm/cycle) for the barrier layer, then sputter the bulk metal.

Electroplating and electroless deposition

A metal is deposited from a liquid electrolyte — electrochemically (driven by an external current) or autocatalytically (electroless). The general mechanism, chemistry, and corrosion/wear applications are covered in Surface finishing; here only the electronics-specific uses matter:

Epitaxy

A single-crystal film is grown on a single-crystal substrate with the same lattice orientation; the film continues the crystal rather than nucleating grains.

Details

How it works, step by step. Atoms arrive at a hot, atomically clean single-crystal surface and find lattice sites that continue the substrate’s periodicity. If the arriving species are supplied as beams in ultra-high vacuum, growth is slow and precisely controlled layer by layer (MBE); if they arrive as gas molecules that decompose on the surface, it is vapor-phase epitaxy (MOVPE, or Si epitaxy from SiH₄). Lattice mismatch between film and substrate creates strain — which is exploited deliberately: compressively strained SiGe in transistor sources/drains boosts hole mobility (see Film stress).

Worked example — silicon epitaxy. A Si wafer is heated to 1100 °C in SiH₄ at low pressure; SiH₄ decomposes at the surface, Si atoms lock into lattice sites, and H₂ desorbs. A 1 µm epi layer grows in ~5 min at ~0.2 µm/min. The layer is doped in-situ (adding diborane or phosphine) to form the wells of a CMOS process.

Main variants:

Example problem

Why must an epitaxial reactor be far cleaner than a CVD oxide reactor, and what happens if a single dust particle lands on the wafer before growth?

Solution
  • Epitaxy copies the substrate’s atomic lattice; any contaminant or particle becomes a nucleation site for misoriented grains or a stacking fault that propagates through the whole layer.
  • A dust particle shadows the lattice: the film grows polycrystalline around it and the defect ruins every device built on that spot — hence front-end fabs run epitaxy in class-1 cleanrooms with in-situ pre-growth HCl or high-temperature bakes to strip the native oxide.

Film stress

Every deposited film is either stretched (tensile) or squeezed (compressive) along its plane. Stress is a first-order process parameter: it bends wafers, cracks or peels films, and — deliberately — changes transistor speed.

Where it comes from:

Measuring it: the wafer bends, and the curvature gives the stress through the Stoney equation:

σf=Es ts26 R tf\sigma_f = \frac{E_s\, t_s^2}{6\, R\, t_f}

where EsE_s and tst_s are the substrate’s Young’s modulus and thickness, RR the measured wafer-bow radius, and tft_f the film thickness. A 500 µm Si wafer with a 1 µm film bowing by 50 µm over 150 mm corresponds to roughly ±100 MPa.

Why it matters in CMOS — strain engineering: mechanical strain deforms the silicon lattice and splits the conduction/valence bands, changing carrier mobility. The effect is used on purpose:

Tensile film → wafer smiles film shrinks: edges curl up (σ > 0) Compressive film → wafer frowns film expands: edges curl down (σ < 0)
Example problem

A 1 µm PECVD nitride is deposited at 400 °C on a 775 µm Si wafer and cools to room temperature. α(Si) = 2.6×10⁻⁶ /K, α(Si₃N₄) = 3.2×10⁻⁶ /K, E(nitride) ≈ 300 GPa. What thermal stress results, and is it tensile or compressive?

Solution
  • ΔT = 400 − 25 = 375 K; Δα = 3.2 − 0.6 ×10⁻⁶… using α(Si₃N₄) − α(Si) = 0.6×10⁻⁶ /K:
  • σ = E Δα ΔT = 300 GPa × 0.6×10⁻⁶ /K × 375 K ≈ 67 MPa, tensile (the nitride contracts less than… it contracts more than silicon, so it ends up stretched).
  • This is small compared with the ±1–3 GPa intrinsic stress of PECVD nitride — which is why the deposition recipe (pressure, RF power, SiH/NH₃ ratio) is the real stress knob, tuned to deliver the desired tensile liner for nMOS mobility.

Comparison of deposition classes

ALD is a special case of CVD (a self-limiting surface-reaction process), so it is listed as a sub-row of CVD. Rates are the primary throughput knob and trade off against film quality: fast films are less conformal, more defective, and more stressed.

ClassMechanismTypical rateTemperatureConformalityTypical film stressTypical applications
CVD (parent class: gas-phase surface reaction)Precursor gases react at the wafer surface; variants differ in how the reaction energy is supplied
  └ Thermal CVDHeat-driven surface reaction10–500 nm/min300–1100 °CGood (step coverage > 90 %)±100 MPa – 1 GPaEpitaxy-adjacent oxides, spacers, TEOS oxides
  └ PECVDPlasma-cracked species react at surface50–1000 nm/min200–400 °CGood−1 GPa (compressive) to +3 GPa (tensile), tunableInterlayer dielectrics, Si₃N₄ stress liners, passivation
  └ ALD (self-limiting CVD)Saturated surface reaction, ~1 monolayer fraction/cycle0.05–0.5 nm/cycle (rate set by cycle time, ~5–10 s)100–400 °CExcellent up to ~10–20:1 ARLow, near-neutral (relaxed, defect-poor films)High-k dielectrics, barrier/liner layers, GAA gates
PVD (sputter / evaporation)Vapor condensation (line-of-sight)1–100 nm/minRoom temp – 400 °CPoor to moderate (step coverage 30–70 %)Tensile (evaporation) to compressive (energetic sputtering), ±0.1–2 GPaMetal interconnects, hard masks, barrier layers
ElectroplatingElectrochemical reduction in solution1–10 µm/hRoom temp – 60 °CGood (additives give bottom-up fill)Tensile, 10–200 MPaCu damascene fill, PCB Cu, TSV filling, bump pads
Epitaxy (MBE / MOVPE / Si)Crystal-lattice-matched growth0.1–10 µm/h (MBE); 0.1–1 µm/min (Si epi)200–1200 °CPlanar only (no step coverage)Set by lattice mismatch (e.g. compressive SiGe on Si)CMOS channels/wells, SiGe stressors, III-V lasers, HEMTs

Conformality: ALD vs. CVD/PVD in a trench

The figure below shows a cross-section of a high-aspect-ratio trench (depth ≈ 10× width). The left panel shows a conformal ALD coating (uniform thickness on all surfaces); the right panel shows a non-conformal CVD/PVD coating (thick on top, pinched at the bottom).

ALD (conformal) uniform thickness CVD / PVD (non-conformal) pinched at bottom

Film quality and process parameters

Film quality is the set of measurable properties that decide whether a deposited layer works in the device: thickness, uniformity, conformality, roughness, interface cleanliness, and stress. Every one of them trades off against deposition rate — the primary throughput knob a process engineer turns. Fast processes (PECVD, sputtering) deliver high throughput but rougher, more stressed, less conformal films; slow ones (ALD, MBE) deliver near-perfect films at a fraction of the wafers per hour.

Details

Thickness and uniformity. Measured by spectroscopic ellipsometry (in-line, non-destructive, 49-point maps). Example: a 300 mm wafer with a nominal 50 nm PECVD SiO₂ film reads 50.2 nm at the center and 49.8 nm at the edge — a spread of 0.4 nm on 50 nm, i.e. 0.8 % uniformity, inside the typical ±2 % CVD spec (ALD specs are tighter, ±1 %).

Step coverage (conformality). Measured by cross-section TEM or SEM on a patterned witness wafer. Example: on a 2:1 via, CVD gives 95 % (bottom thickness / top thickness), ALD gives 99 %, sputtering 40 % — which is why sputtered barrier layers need ALD liners in deep vias.

Deposition rate. Measured from film thickness divided by deposition time (nm/min, or nm/cycle for ALD). Example: the same SiO₂ film above grows at 100 nm/min, so a 25-wafer batch takes ~5 min of deposition plus pump/heat-up overhead; an ALD 5 nm HfO₂ at 0.12 nm/cycle and 8 s/cycle takes ~55 min of pure cycling. Rate is the reason PECVD, not ALD, fills thick dielectric layers, and ALD, not PECVD, gates the transistor.

Surface roughness. Measured by AFM (RMS). Example: an ALD Al₂O₃ film reads 0.2 nm RMS — atomically smooth because each cycle re-smooths the surface — while a sputtered Al film reads 3–5 nm RMS because grains grow competitively.

Interface quality. Cross-section TEM and XPS check for intermixing or contamination at the film/substrate boundary. Example: a poor pre-deposition clean leaves ~1 nm of native oxide under a gate electrode, shifting the threshold voltage of every transistor on the wafer.

Stress. Measured by wafer-bow (Stoney, see Film stress). Example: a PECVD nitride liner is tuned from −1 GPa (compressive) to +3 GPa (tensile) by changing the SiH₄/NH₃ ratio and RF power, without changing its function as a diffusion barrier.

Interactive simulation

Quiz

A 3 nm GAA (gate-all-around) transistor requires a conformal high-k dielectric (HfO₂, 5 nm thick) to coat the nanowire channel (aspect ratio 10:1). Which deposition process is appropriate, and how many cycles does it take?

How to solve it
Solution
  1. Requirement: 5 nm HfO₂ with < 1 % thickness variation over a 10:1 aspect-ratio nanowire.
  2. Process: ALD. CVD and PVD cannot achieve the required conformality at this aspect ratio. ALD’s self-limiting reaction deposits a fixed amount per cycle regardless of exposure time, giving uniform thickness on every surface.
  3. Precursors: HfCl₄ + H₂O (or O₃) as the co-reactant. Each cycle deposits ~0.1–0.15 nm of HfO₂ (typical for HfCl₄/H₂O at 300 °C); 5 nm / 0.12 nm per cycle ≈ 42 cycles. (TDMAH-based precursors give ~0.1–0.15 nm/cycle as well, with better thermal stability.)
  4. Temperature: 250–350 °C (compatible with back-end-of-line thermal budgets).
  5. Verification: cross-section TEM for thickness and step coverage; spectroscopic ellipsometry for in-line thickness monitoring; wafer-bow metrology to confirm the film stress is acceptable.

Parent

This page is a class in the Electronics topic, which is a subtopic of Manufacturing.

Deposition adds a thin film of conductor, insulator, or semiconductor material onto a substrate. It is the material-adding step in electronics fabrication: every metal wire, dielectric layer, and semiconductor channel on a chip is deposited.

Authoritative sources

Utility

Role in the fabrication flow

A chip is built layer by layer in a repeating cycle:

  1. Lithography — pattern a resist on the wafer.
  2. Deposition — add the material (this page).
  3. Etching — remove material outside the pattern.
  4. Planarization — flatten the surface (CMP, see Interconnect and packaging).
  5. Repeat for the next layer.

Each cycle adds one functional layer (a gate oxide, a metal interconnect, a well region, etc.). After 50–100 cycles the wafer contains the full 3D stack of a modern logic or memory chip. Deposition is the step that actually adds material; without it the etch and planarization steps have nothing to shape.

Key concepts

Chemical vapor deposition (CVD)

A gas-phase reaction deposits a solid film on the substrate surface.

Details

Physical vapor deposition (PVD)

A solid source is vaporized and condensed on the substrate.

Details

Electroplating and electroless deposition

A metal is deposited electrochemically or by chemical reduction. This section covers the electronics-specific applications; for the general manufacturing context (corrosion resistance, wear protection) see Surface finishing.

Details

Epitaxy

A single-crystal film is grown on a single-crystal substrate with the same lattice orientation.

Details

Comparison of deposition classes

ClassMechanismTemperatureConformalityTypical thicknessTypical applications
CVD / PECVDGas-phase surface reaction100–1100 °CGood (step coverage > 90 %)10 nm – 10 µmGate oxides, spacers, interlayer dielectrics
ALDSelf-limiting surface reaction, 1 layer/cycle100–400 °CExcellent up to ~10–20:1 AR1 – 100 nmHigh-k dielectrics, barrier layers, GAA gates
PVD (sputter / evap)Vapor condensation (line-of-sight)Room temp – 400 °CPoor to moderate (step coverage 30–70 %)10 nm – 1 µmMetal interconnects, hard masks, barrier layers
ElectroplatingElectrochemical reduction in solutionRoom temp – 60 °CGood (electromigration fills from bottom)1 µm – 1 mmPCB Cu, TSV filling, wire bond pads
Epitaxy (MBE / MOVPE / Si)Crystal-lattice-matched growth200–1200 °CPlanar only (no step coverage)10 nm – 10 µmCMOS channels, III-V lasers, HEMTs

Conformality: ALD vs. CVD/PVD in a trench

The figure below shows a cross-section of a high-aspect-ratio trench (depth ≈ 10× width). The left panel shows a conformal ALD coating (uniform thickness on all surfaces); the right panel shows a non-conformal CVD/PVD coating (thick on top, pinched at the bottom).

ALD (conformal) uniform thickness CVD / PVD (non-conformal) pinched at bottom

Film quality metrics

Details

Interactive simulation

Example problem

A 3 nm GAA (gate-all-around) transistor requires a conformal high-k dielectric (HfO₂, 5 nm thick) to coat the nanowire channel (aspect ratio 10:1). Which deposition process is appropriate?

Solution
  1. Requirement: 5 nm HfO₂ with < 1 % thickness variation over a 10:1 aspect-ratio nanowire.
  2. Process: ALD. CVD and PVD cannot achieve the required conformality at this aspect ratio. ALD’s self-limiting reaction ensures one atomic layer per cycle, giving uniform thickness regardless of geometry.
  3. Precursors: HfCl₄ + H₂O (or O₃) as the co-reactant. Each cycle deposits ~0.05 nm of HfO₂ (0.5 Å/cycle, typical for HfCl₄/H₂O at 300 °C); ~100 cycles give 5 nm. (TDMAH-based precursors give ~0.07–0.16 nm/cycle, requiring fewer cycles.)
  4. Temperature: 250–350 °C (compatible with back-end-of-line processing).
  5. Verification: Cross-section TEM to measure thickness and step coverage; spectroscopic ellipsometry for in-line thickness monitoring.

Parent

This page is a class in the Electronics topic, which is a subtopic of Manufacturing.

Parent

This page is a class in the Electronics topic, which is a subtopic of Manufacturing.