Lithography §
Lithography transfers a geometric pattern from a mask (or a digital source) onto a photoresist-coated substrate using light, electron beams, ion beams, or a physical stamp. It is the defining step in semiconductor fabrication: every transistor, wire, and via on a chip is defined by a lithography exposure.
Authoritative sources
Utility §
Lithography is the bottleneck of semiconductor manufacturing for three interlocking reasons:
- It sets the minimum feature size. The resolution of the lithography tool determines the smallest transistor gate, the narrowest interconnect, and the smallest via. Every other process step (etch, deposition, planarization) is designed around the pattern that lithography defines.
- It is the most capital-intensive step. A single low-NA EUV scanner (NA 0.33) costs approximately $180–240 M; a High-NA EUV scanner (NA 0.55) costs roughly $380 M. At leading-edge nodes, lithography accounts for a large fraction of total fab cost, both in equipment and in the mask sets required for multi-patterning.
- It determines transistor count per die. Historically, Dennard scaling (1974) assumed that feature dimensions could be scaled by a constant factor while maintaining the same power density, doubling transistor count every two years (Moore’s law). Lithography is the step that makes that scaling physically possible—or impossible.
When the diffraction limit of a given wavelength is reached, the industry must either shorten the wavelength (ArF → EUV), increase the numerical aperture (low-NA → high-NA EUV), or add patterning steps (multi-patterning). Each option carries a steep cost, which is why lithography drives the pace and economics of the entire semiconductor industry.
Key concepts §
Resolution limit (fundamental physics) §
The minimum resolvable feature size in optical lithography is governed by the Rayleigh criterion:
where is the minimum resolvable half-pitch, is a process factor (typically 0.25–0.35), is the wavelength of the illumination, and is the numerical aperture of the projection optics. The depth of focus is:
with a process factor of order 1. Resolution and depth of focus are in direct tension: increasing NA improves resolution but shrinks the focus window.
Why diffraction limits resolution
A lens is a finite-aperture system. When a point source is imaged through a circular aperture, the image is not a point but an Airy disk: a bright central spot surrounded by concentric rings of decreasing intensity. The radius of the first dark ring is
Two point sources are resolvable only when the first minimum of one Airy disk falls at or beyond the center of the other (the Rayleigh criterion). This gives a minimum separation of .
The underlying reason is that the finite aperture of the lens truncates the spatial frequency spectrum of the image. A perfect image of an arbitrary pattern would require all spatial frequencies up to infinity; a lens with numerical aperture NA can only transmit frequencies up to . Features with spatial frequency above this cutoff are simply lost, setting a hard lower bound on the smallest printable feature.
This is the Abbe diffraction limit: no optical system can focus light to a spot smaller than approximately . It is not an engineering limitation that better lenses can overcome; it is a consequence of the wave nature of light.
Photolithography (optical) §
A patterned mask is illuminated with UV light; the light passes through the transparent regions of the mask and exposes the photoresist on the wafer. After development, the resist pattern is transferred into the underlying film by Etching.
Optical path (schematic):
Details
- Wavelengths and generations:
| Generation | Wavelength | NA | Typical k₁ | Min. half-pitch |
|---|---|---|---|---|
| g-line | 436 nm | 0.6 | 0.35 | ≈ 254 nm |
| i-line | 365 nm | 0.6 | 0.35 | ≈ 213 nm |
| KrF | 248 nm | 0.6 | 0.30 | ≈ 124 nm |
| ArF dry | 193 nm | 0.75 | 0.28 | ≈ 72 nm |
| ArF immersion | 193 nm (in water, n = 1.44) | 1.35 | 0.25 | ≈ 36 nm |
| EUV (low-NA) | 13.5 nm | 0.33 | 0.30 | ≈ 12 nm |
| EUV (high-NA) | 13.5 nm | 0.55 | 0.30 | ≈ 7.4 nm |
- EUV lithography: 13.5 nm light is generated by laser-ablated tin droplets in a vacuum chamber and focused by a multi-layer Mo/Si Bragg reflector (no glass optics exist at this wavelength). Enables 7 nm and below nodes.
- High-NA EUV: The next generation uses a numerical aperture of 0.55 (versus 0.33 for standard EUV), improving resolution by a factor of . Each tool costs approximately $380 M. High-NA EUV is targeted for sub-2 nm logic nodes (expected deployment 2025–2027).
- Immersion: In ArF immersion, a layer of ultrapure water (refractive index 1.44) fills the gap between the final lens element and the wafer, effectively increasing NA from 0.75 to 1.35 without changing the wavelength.
- Multi-patterning: At nodes below the single-exposure resolution limit, the same area is exposed multiple times with different masks to create features smaller than the diffraction limit. See the diagram below.
Resolution vs. wavelength (each generation):
Multi-patterning (how pitch is halved):
Electron-beam lithography (EBL) §
A focused electron beam writes the pattern directly onto the resist, without a mask. Because electrons have a de Broglie wavelength of picometers at typical beam energies (100 keV → nm), diffraction is negligible and resolution is set by beam spot size and scattering.
Details
- Resolution: < 10 nm (down to ~1 nm with advanced tools). Used for mask fabrication and R&D.
- Throughput: very slow (serial writing). A single 300 mm mask can take hours to days.
- Proximity effect: forward- and back-scattered electrons expose neighboring areas; correction algorithms (e.g., PROX) are required.
- Use: mask blanks for photolithography, nanophotonic structures, quantum devices, research prototyping.
- Variants: variable-shaped beam (VSB) EBL writes rectangles at high speed; multi-beam EBL (e.g., Vistec, Elionix) uses hundreds of beams in parallel to improve throughput.
Other methods §
Beyond optical and electron-beam lithography, several distinct techniques complete the landscape:
X-ray lithography
- Wavelength: ~0.5 nm (soft X-rays), far shorter than EUV.
- Principle: X-rays pass through a phase mask (no absorption mask needed at this wavelength) and expose a resist on a wafer in close proximity to the mask (no projection lens; demagnification is achieved geometrically).
- Status: Demonstrated at IBM and others in the 1990s–2000s; not adopted for high-volume manufacturing because EUV proved more practical. Remains of interest for mask inspection and specialized applications.
Ion-beam lithography
- Principle: A focused ion beam (typically Ga⁺ or He⁺) writes the pattern directly, analogous to EBL but with ions instead of electrons. Ions have negligible de Broglie wavelength, so there is no diffraction limit.
- Resolution: ~1–5 nm (limited by beam spot and ion-induced damage).
- Advantage: Ions implant into the substrate, enabling direct material modification without a separate etch step.
- Use: Focused ion beam (FIB) systems are used for mask repair, cross-sectioning, and nanoscale prototyping. Not used for high-volume IC patterning due to low throughput.
Nanoimprint lithography (NIL)
- Principle: A physical stamp (mold) with the inverse pattern is pressed into a thermoplastic or UV-curable resist, mechanically transferring the pattern. No light, no electrons, no ions.
- Resolution: < 10 nm demonstrated; limited by stamp fabrication and alignment.
- Advantage: No diffraction limit; very low cost per wafer once the stamp is made.
- Limitations: Alignment for multi-layer stacking is challenging; defect control at high volume is difficult; throughput is lower than optical scanners.
- Use: Research, some display backplane manufacturing, and potential future high-volume applications.
Resolution Enhancement Techniques (RET) §
The naive Rayleigh criterion assumes a perfect mask and ideal optics. In practice, modern fabs push well beyond the “first-order” limit using a suite of Resolution Enhancement Techniques that modify the mask, the illumination, or both. These techniques are a major part of what makes lithography the most expensive and complex step in the fab.
Details
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Optical Proximity Correction (OPC): The mask geometry is deliberately distorted (serifs, hammerheads, line-end extensions) so that the image on the wafer matches the intended pattern. OPC compensates for the fact that isolated lines, dense lines, and corners all diffract differently. Computed by rigorous electromagnetic simulation of the optical system.
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Phase-Shift Masks (PSM): Adjacent transparent regions of the mask are given a 180° phase difference. The resulting destructive interference at the boundary sharpens the image edge, effectively improving resolution by ~20–30% without changing λ or NA. Types: attenuated PSM (aTSM) and alternating PSM (aPSM).
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Off-Axis Illumination (OAI): The illumination is shifted or shaped (annular, quadrupole, dipole) so that only specific diffraction orders reach the lens. This improves image contrast for particular pattern types (e.g., dense line/space) at the cost of other pattern types. Often combined with OPC.
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Inverse Lithography Technology (ILT): The mask is treated as a grid of pixels (or sub-pixels), and an optimization algorithm (often gradient-based or adjoint-method) computes the pixel intensities that produce the target wafer image. ILT subsumes OPC and can achieve the best possible image fidelity for a given optical system, at the cost of enormous computational resources and mask complexity.
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Hybrid approaches: Modern leading-edge layers typically combine OAI + ILT + advanced resist + multi-patterning. The choice of RET stack is a co-optimization problem involving the optical system, the resist, and the downstream Etching process.
Photoresist §
Photoresist is the light-sensitive (or particle-sensitive) polymer that records the pattern. It is a consumable material used in photolithography, EBL, and other exposure-based methods—not a lithography technique itself.
Details
- Positive resist: exposed regions become soluble in developer and are washed away. Most common in IC manufacturing (e.g., chemically amplified resists based on polycaprolactone).
- Negative resist: exposed regions cross-link and become insoluble. Used for high-resolution or high-aspect-ratio structures (e.g., SU-8 for MEMS).
- Thickness: 0.1–2 µm for IC; up to 100 µm for thick-film or MEMS.
- Coating: spin-coating at 2000–5000 rpm produces a uniform film; post-apply bake (PAB) removes residual solvent.
- EUV resists: require new chemistries because 13.5 nm photons are absorbed in the top ~50 nm of the resist, generating secondary electrons that do the actual exposure. Stochastic effects (shot noise) become significant at the smallest features.
- Role in the fab flow: After development, the resist pattern serves as a mask for Etching of the underlying Deposition layer. The resist is then stripped and the cycle repeats for the next layer.
Fab flow context §
Lithography is one step in a repeating cycle that builds a chip layer by layer:
A modern logic chip requires 50–100+ such cycles. Lithography is performed 20–40 times per wafer (more with multi-patterning). The Etching step transfers the resist pattern into the deposited film; the Deposition step adds the next layer of material; CMP (chemical-mechanical planarization) flattens the surface before the next lithography cycle.
Example problem §
A 5 nm logic chip has a dense gate layer with a half-pitch of 21 nm. Compare the patterning options:
- ArF immersion (λ = 193 nm, NA = 1.35, k₁ = 0.25): single-exposure resolution is nm. Since 21 nm < 35.7 nm, multi-patterning is required. How many exposures?
- EUV low-NA (λ = 13.5 nm, NA = 0.33, k₁ = 0.30): single-exposure resolution is nm. Can 21 nm be achieved in a single exposure?
- Compare the number of masks, alignment steps, and relative cost.
Solution
ArF immersion:
- Single-exposure resolution: nm.
- Required half-pitch: 21 nm. Ratio: .
- Since the ratio is between 1 and 2, double patterning (2×) is needed: two masks, two exposures, plus a spacer etch step to create the intermediate lines. Total: 2 litho exposures + 1 spacer deposition + 1 spacer etch + 2 alignment steps.
- If the required pitch were tighter (e.g., 15 nm), triple patterning (3×) would be needed: 3 masks, 3 exposures, 3 alignment steps.
EUV low-NA:
- Single-exposure resolution: nm.
- Required half-pitch: 21 nm. Since 21 nm > 12.3 nm, a single exposure suffices with a comfortable margin (, well within the 0.25–0.35 design target when accounting for process margin).
- Total: 1 mask, 1 exposure, 1 alignment step.
Comparison:
| Option | Masks | Exposures | Alignment steps | Extra steps | Relative cost |
|---|---|---|---|---|---|
| ArF immersion 2× | 2 | 2 | 2 | Spacer dep + etch | ~2× single EUV |
| EUV single | 1 | 1 | 1 | None | 1× (baseline) |
Conclusion: EUV single-exposure is strongly preferred for the 21 nm half-pitch gate layer: it halves the mask count, eliminates the spacer process, and reduces alignment error accumulation. ArF immersion multi-patterning remains viable for less-critical layers where EUV is not yet cost-effective or where the required pitch is above ~25 nm.
Interactive simulation §
Parent §
This page is a class in the Electronics topic, which is a subtopic of Manufacturing.